Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
Inverter
Number of Elements per Chip
1
Schmitt Trigger Input
No
Maximum Propagation Delay Time @ Maximum CL
4.2 ns @ 3.3 V
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
5
Logic Family
LVC
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Supply Voltage
5.5 V
Height
0.9mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+85 °C
Length
2mm
Width
1.25mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
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BD 0.295
Each (In a Pack of 5) (Exc. Vat)
BD 0.325
Each (In a Pack of 5) (Including VAT)
5
BD 0.295
Each (In a Pack of 5) (Exc. Vat)
BD 0.325
Each (In a Pack of 5) (Including VAT)
5
Buy in bulk
quantity | Unit price | Per Pack |
---|---|---|
5 - 45 | BD 0.295 | BD 1.475 |
50 - 95 | BD 0.240 | BD 1.200 |
100 - 245 | BD 0.220 | BD 1.100 |
250 - 495 | BD 0.205 | BD 1.025 |
500+ | BD 0.190 | BD 0.950 |
Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
Inverter
Number of Elements per Chip
1
Schmitt Trigger Input
No
Maximum Propagation Delay Time @ Maximum CL
4.2 ns @ 3.3 V
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
5
Logic Family
LVC
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Supply Voltage
5.5 V
Height
0.9mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+85 °C
Length
2mm
Width
1.25mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22