Technical Documents
Specifications
Brand
MicrochipProduct Type
Microcontroller
Series
tinyAVR
Package Type
SOIC
Pin Count
14
Device Core
AVR
Program Memory Size
16kB
Maximum Clock Frequency
20MHz
RAM Size
2kB
Maximum Supply Voltage
2.7V
Number of Programmable I/Os
22
DACs
8 bit
Minimum Operating Temperature
-40°C
Analogue Comparators
3
Maximum Expanded Memory Size
16kB
Maximum Operating Temperature
125°C
Standards/Approvals
No
Number of Timers
4
Instruction Set Architecture
Harvard
Automotive Standard
No
ADCs
10 bit
Program Memory Type
FLASH
Product Details
The Microchip microcontrollers uses the AVR® processor with hardware multiplier, running at up to 20 MHz, with 16 KB Flash, 2 KB of SRAM, and 256 bytes of EEPROM in a 14 pin package. It uses latest technologies with a flexible, low power architecture, including Event System, accurate analog features, and Core Independent Peripherals (CIPs). Capacitive touch interfaces with Driven Shield+ and Boost Mode technologies are supported with the integrated Peripheral Touch Controller (PTC).
Stock information temporarily unavailable.
P.O.A.
Each (Supplied in a Tube) (Exc. Vat)
Production pack (Tube)
10
P.O.A.
Each (Supplied in a Tube) (Exc. Vat)
Stock information temporarily unavailable.
Production pack (Tube)
10
Technical Documents
Specifications
Brand
MicrochipProduct Type
Microcontroller
Series
tinyAVR
Package Type
SOIC
Pin Count
14
Device Core
AVR
Program Memory Size
16kB
Maximum Clock Frequency
20MHz
RAM Size
2kB
Maximum Supply Voltage
2.7V
Number of Programmable I/Os
22
DACs
8 bit
Minimum Operating Temperature
-40°C
Analogue Comparators
3
Maximum Expanded Memory Size
16kB
Maximum Operating Temperature
125°C
Standards/Approvals
No
Number of Timers
4
Instruction Set Architecture
Harvard
Automotive Standard
No
ADCs
10 bit
Program Memory Type
FLASH
Product Details
The Microchip microcontrollers uses the AVR® processor with hardware multiplier, running at up to 20 MHz, with 16 KB Flash, 2 KB of SRAM, and 256 bytes of EEPROM in a 14 pin package. It uses latest technologies with a flexible, low power architecture, including Event System, accurate analog features, and Core Independent Peripherals (CIPs). Capacitive touch interfaces with Driven Shield+ and Boost Mode technologies are supported with the integrated Peripheral Touch Controller (PTC).