Technical Document
Specifications
Brand
NexperiaLogic Family
LVT
Logic Function
Buffer, Line Driver
Number of Channels
4
Schmitt Trigger Input
No
Input Type
Single Ended
Output Type
3 State
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
14
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
64mA
Maximum Propagation Delay Time @ Maximum CL
2.9 ns @ 3.3 V
Dimensions
5.1 x 4.5 x 0.95mm
Maximum Operating Supply Voltage
3.6 V
Height
0.95mm
Width
4.5mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
2.7 V
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
5.1mm
Country of Origin
Thailand
Product details
74LVT Family, Nexperia
Low-Voltage BiCMOS Technology Logic
Operating Voltage 2.7 to 3.6
Compatibility: Input LVTTL/TTL, Output LVTTL
74LVT Family
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BD 0.185
Each (In a Tube of 96) (Exc. Vat)
BD 0.203
Each (In a Tube of 96) (Including VAT)
96
BD 0.185
Each (In a Tube of 96) (Exc. Vat)
BD 0.203
Each (In a Tube of 96) (Including VAT)
96
Buy in bulk
quantity | Unit price | Per Tube |
---|---|---|
96 - 384 | BD 0.185 | BD 17.760 |
480 - 1824 | BD 0.160 | BD 15.360 |
1920 - 4704 | BD 0.140 | BD 13.440 |
4800+ | BD 0.135 | BD 12.960 |
Technical Document
Specifications
Brand
NexperiaLogic Family
LVT
Logic Function
Buffer, Line Driver
Number of Channels
4
Schmitt Trigger Input
No
Input Type
Single Ended
Output Type
3 State
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
14
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
64mA
Maximum Propagation Delay Time @ Maximum CL
2.9 ns @ 3.3 V
Dimensions
5.1 x 4.5 x 0.95mm
Maximum Operating Supply Voltage
3.6 V
Height
0.95mm
Width
4.5mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
2.7 V
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
5.1mm
Country of Origin
Thailand
Product details
74LVT Family, Nexperia
Low-Voltage BiCMOS Technology Logic
Operating Voltage 2.7 to 3.6
Compatibility: Input LVTTL/TTL, Output LVTTL