Technical Document
Specifications
Brand
onsemiLogic Family
LVT
Logic Function
Bus Transceiver
Number of Elements per Chip
1
Number of Channels per Chip
8
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
20
Input Level
LVTTL
Output Level
LVTTL
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
64mA
Maximum Propagation Delay Time @ Maximum CL
4 ns @ 2.7 V
Minimum Operating Temperature
-40 °C
Dimensions
6.5 x 4.4 x 0.9mm
Minimum Operating Supply Voltage
2.7 V
Height
0.9mm
Width
4.4mm
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
6.5mm
Maximum Operating Supply Voltage
3.6 V
Product details
74LVT Family, Fairchild Semiconductor
Low-Voltage BiCMOS Technology Logic
Operating Voltage 2.7 to 3.6
Compatibility: Input LVTTL/TTL, Output LVTTL
74LVT Family
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BD 0.815
Each (In a Tube of 73) (Exc. Vat)
BD 0.897
Each (In a Tube of 73) (inc. VAT)
73
BD 0.815
Each (In a Tube of 73) (Exc. Vat)
BD 0.897
Each (In a Tube of 73) (inc. VAT)
73
Buy in bulk
quantity | Unit price | Per Tube |
---|---|---|
73 - 73 | BD 0.815 | BD 59.495 |
146 - 438 | BD 0.625 | BD 45.625 |
511 - 949 | BD 0.560 | BD 40.880 |
1022 - 2482 | BD 0.450 | BD 32.850 |
2555+ | BD 0.430 | BD 31.390 |
Technical Document
Specifications
Brand
onsemiLogic Family
LVT
Logic Function
Bus Transceiver
Number of Elements per Chip
1
Number of Channels per Chip
8
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
20
Input Level
LVTTL
Output Level
LVTTL
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
64mA
Maximum Propagation Delay Time @ Maximum CL
4 ns @ 2.7 V
Minimum Operating Temperature
-40 °C
Dimensions
6.5 x 4.4 x 0.9mm
Minimum Operating Supply Voltage
2.7 V
Height
0.9mm
Width
4.4mm
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
6.5mm
Maximum Operating Supply Voltage
3.6 V
Product details
74LVT Family, Fairchild Semiconductor
Low-Voltage BiCMOS Technology Logic
Operating Voltage 2.7 to 3.6
Compatibility: Input LVTTL/TTL, Output LVTTL