Texas Instruments SN74LVC2G125DCUR Dual Bus Buffer, 8-Pin US
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Mounting Type
Surface Mount
Package Type
US
Pin Count
8
Maximum Propagation Delay Time @ Maximum CL
4.2 ns @ 5 V
Dimensions
2.1 x 2.4 x 0.8mm
Maximum Operating Supply Voltage
5.5 V
Width
2.4mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Temperature
+125 °C
Propagation Delay Test Condition
50pF
Length
2.15mm
Height
0.8mm
Product details
74LVC Family Inverters & Buffers, Texas Instruments
Texas Instruments range of Inverters and Buffers from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family
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BD 247.500
BD 0.082 Each (On a Reel of 3000) (Exc. Vat)
BD 272.250
BD 0.090 Each (On a Reel of 3000) (inc. VAT)
3000
BD 247.500
BD 0.082 Each (On a Reel of 3000) (Exc. Vat)
BD 272.250
BD 0.090 Each (On a Reel of 3000) (inc. VAT)
3000
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Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Mounting Type
Surface Mount
Package Type
US
Pin Count
8
Maximum Propagation Delay Time @ Maximum CL
4.2 ns @ 5 V
Dimensions
2.1 x 2.4 x 0.8mm
Maximum Operating Supply Voltage
5.5 V
Width
2.4mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Temperature
+125 °C
Propagation Delay Test Condition
50pF
Length
2.15mm
Height
0.8mm
Product details
74LVC Family Inverters & Buffers, Texas Instruments
Texas Instruments range of Inverters and Buffers from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family
Ideate. Create. Collaborate
JOIN FOR FREE
No hidden fees!
- Download and use our DesignSpark software for your PCB and 3D Mechanical designs
- View and contribute website content and forums
- Download 3D Models, Schematics and Footprints from more than a million products