Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
D Type
Input Type
Single Ended
Output Signal Type
Differential
Triggering Type
Positive Edge
Polarity
Inverting, Non-Inverting
Mounting Type
Surface Mount
Package Type
VSSOP
Pin Count
8
Set/Reset
Yes
Number of Elements per Chip
1
Maximum Propagation Delay Time @ Maximum CL
7.2 ns @ 3.3 V
Maximum Operating Supply Voltage
5.5 V
Dimensions
2.3 x 2 x 0.85mm
Width
2mm
Minimum Operating Supply Voltage
1.65 V
Minimum Operating Temperature
-40 °C
Height
0.85mm
Propagation Delay Test Condition
50pF
Maximum Operating Temperature
+125 °C
Length
2.3mm
Product details
74LVC2G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
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BD 0.255
Each (Supplied on a Reel) (Exc. Vat)
BD 0.281
Each (Supplied on a Reel) (inc. VAT)
Production pack (Reel)
10
BD 0.255
Each (Supplied on a Reel) (Exc. Vat)
BD 0.281
Each (Supplied on a Reel) (inc. VAT)
Production pack (Reel)
10
Buy in bulk
quantity | Unit price | Per Reel |
---|---|---|
10 - 40 | BD 0.255 | BD 2.550 |
50 - 90 | BD 0.205 | BD 2.050 |
100 - 190 | BD 0.175 | BD 1.750 |
200 - 390 | BD 0.145 | BD 1.450 |
400+ | BD 0.140 | BD 1.400 |
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
D Type
Input Type
Single Ended
Output Signal Type
Differential
Triggering Type
Positive Edge
Polarity
Inverting, Non-Inverting
Mounting Type
Surface Mount
Package Type
VSSOP
Pin Count
8
Set/Reset
Yes
Number of Elements per Chip
1
Maximum Propagation Delay Time @ Maximum CL
7.2 ns @ 3.3 V
Maximum Operating Supply Voltage
5.5 V
Dimensions
2.3 x 2 x 0.85mm
Width
2mm
Minimum Operating Supply Voltage
1.65 V
Minimum Operating Temperature
-40 °C
Height
0.85mm
Propagation Delay Test Condition
50pF
Maximum Operating Temperature
+125 °C
Length
2.3mm
Product details
74LVC2G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS