Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer, Driver
Number of Channels per Chip
3
Input Type
Single Ended
Output Type
Open Drain
Polarity
Inverting
Mounting Type
Surface Mount
Package Type
SM
Pin Count
8
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
9.8 ns@ 30 pF
Dimensions
3.15 x 2.9 x 1.2mm
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
30pF
Product details
74LVC3G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
Stock information temporarily unavailable.
BD 5.509
BD 0.367 Each (Supplied as a Tape) (Exc. Vat)
BD 6.060
BD 0.404 Each (Supplied as a Tape) (inc. VAT)
Standard
15
BD 5.509
BD 0.367 Each (Supplied as a Tape) (Exc. Vat)
BD 6.060
BD 0.404 Each (Supplied as a Tape) (inc. VAT)
Stock information temporarily unavailable.
Standard
15
| Quantity | Unit price | Per Tape |
|---|---|---|
| 15 - 30 | BD 0.367 | BD 5.509 |
| 45 - 75 | BD 0.305 | BD 4.576 |
| 90 - 435 | BD 0.266 | BD 3.983 |
| 450 - 2985 | BD 0.220 | BD 3.305 |
| 3000+ | BD 0.175 | BD 2.627 |
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer, Driver
Number of Channels per Chip
3
Input Type
Single Ended
Output Type
Open Drain
Polarity
Inverting
Mounting Type
Surface Mount
Package Type
SM
Pin Count
8
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
9.8 ns@ 30 pF
Dimensions
3.15 x 2.9 x 1.2mm
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
30pF
Product details
74LVC3G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
