Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
Inverter
Output Type
CMOS
Number of Elements per Chip
1
Schmitt Trigger Input
No
Maximum Propagation Delay Time @ Maximum CL
3.7 ns @ 5 V
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
5
Logic Family
LVC
Dimensions
3.05 x 1.75 x 1.3mm
Maximum Operating Supply Voltage
5.5 V
Height
1.3mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
3.05mm
PRICED TO CLEAR
Yes
Width
1.75mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC Family Inverters & Buffers, Texas Instruments
Texas Instruments range of Inverters and Buffers from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family
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P.O.A.
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P.O.A.
50
Technical Document
Specifications
Brand
Texas InstrumentsLogic Function
Inverter
Output Type
CMOS
Number of Elements per Chip
1
Schmitt Trigger Input
No
Maximum Propagation Delay Time @ Maximum CL
3.7 ns @ 5 V
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
5
Logic Family
LVC
Dimensions
3.05 x 1.75 x 1.3mm
Maximum Operating Supply Voltage
5.5 V
Height
1.3mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
3.05mm
PRICED TO CLEAR
Yes
Width
1.75mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC Family Inverters & Buffers, Texas Instruments
Texas Instruments range of Inverters and Buffers from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22